The P2 is a 2 x 10/100 NIC + Crypto carrier board for the RPI-CM1/3/3+.
Perfect as a LAN/WAN router device with edge processing capacity. Perhaps add an LTE modem and PoE-PSE expansion board for an IoT gateway with two PoE devices.
P2 requires an imaged RPI-CM1/3/3+ with eMMC (ie non-LITE versions).
See these raspberrypi.org links for details and purchasing information :
RPI-CM3+
RPI-CM3
RPI-CM1
Raspberry Pi guarantee availability of CM1, CM3 until at least January 2023.
Raspberry Pi guarantee availability of CM3+ until at least January 2026.
The RPI-CM cannot be imaged using a PiGWay. If your RPI-CM is not pre-imaged you could use the Compute Module Development Kit.
As the PiGWay is headless, your image will need to enable networking & SSH or a UART console to connect via a commandline.
Note : RPI 40-pin UART pins are 3.3V, a level-shifter maybe required. We use a UART console with SparkFun's FTDI Basic Breakout - 3.3V.
P2 has two high-Performance 10/100 ethernet controllers, each with their own EEPROM for configuration :
Ethernet magnetics' taps for PoE are exported to 2.54mm (0.1") headers. These can be used to either :
i) power the device via PoE (PD), or
ii) to power externally connected PoE devices (PSE).
See the .brd file mechanical positioning.
P2 includes Microchip's ATECC608A chip for secure key generation, storage and signing.
Communication with the chip is via RPI's i2c0 @ address 0x60. i2c0 must be enabled in /boot/config.txt by adding the line:
dtparam=i2c0=on
The complete datasheet for the ATECC608A is only available from Microchip under NDA. However, their CryptoAuthentication Library is hosted at GitHub
P2 exports two USB2.0 to 2.54mm (0.1") headers for internal expansion.
Each 5V power rail is controlled by a high-side power switch with overcurrent protection @ 1A. Expansion boards requiring additional current should source it from either the power header or 5V pins of the 40-pin header.
See the .brd file for mechanical positioning.
A USB expansion board is available for those requiring a standard USB type A connector.
P2's 40-pin expansion header is pin compatible with the RPI's 40-pin GPIO header and will accept RPI HATs with acceptable dimensions.
Expansion header's ground pins are directly connected to the carrier boards digital ground plane.
3.3V pins current draw should not exceed 100mA. If additional current is required you should use the 5V rail and step-down as appropriate.
5V pins are directly connected to the power header's 5V. Available current is therefore dependent on the connected power supply, but must not exceed 2A (PCB traces).
The remaining GPIO pins are 3.3V. Individual GPIO pin current draw should not exceed 16mA, and the total current from all GPIO pins should not exceed 51mA.
P2 has four LEDs. LED1 (green) indicates power, the remaining three LEDs are user controllable.
Controllable LEDs are attached to the following RPI-CM's GPIO pins:
#!/bin/sh
ss=`28 29 30`
for s in $ss; do
echo $s > /sys/class/gpio/export
echo high > /sys/class/gpio/gpio$s/direction
done
In its default configuration, the P2 requires a clean 5VDC power source. The carrier board requires a minimum of 2A.
The power required for any particular configuration will depend on the total power consumption of any installed expansion boards, HATs and/or USB devices.
A 2.1mm, positive centre, barrel type power jack is included. This power jack can be isolated by removing the power header's jumper (+ only). Once isolated, the jack can be reused by power expansion boards to support a variety of voltages (eg 48VDC for PoE PSE).
See the .brd file for mechanical positioning.
A suitable power supply for regular loads is the Meanwell GE24I05-P1J and the appropriate plug:
Australia
US
European
UK
PiGWays schematics, .brd files and source code are available under a GPLv3 license. See our GitHub repository (2021Q1).
Commercial licenses are also available for those wishing to utilise our intellectual property (IP) in proprietary solutions.
Dimensions: 90.20 x 92.71 x 18 mm (W x D x H)
Weight : 75g
See the .brd file for details and mechanical positioning.